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Question # 4

When programming in C, how many bytes of stack are needed to pass parameters when calling the following function?

int foo( int arg_a, int arg_b, int arg_c )

A.

0

B.

4

C.

8

D.

12

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Question # 5

In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?

A.

D0..D31 and S0..S31 are separate register banks

B.

D0..D31 overlap with S0..S63

C.

D0..D15 overlap with S0..S31, and D16..D31 do not overlap with any single-precision registers

D.

D0 overlaps with S0, D1 with S1 etc. up to D31 and S31

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Question # 6

Which of the following is an advantage of the single-step debug technique?

A.

It allows a complete trace of real-time program execution to be captured

B.

It reduces the number of pins required to connect the debugger to the processor

C.

It allows examination of the system state before and after execution of a statement

D.

It requires only one change to the program source code

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Question # 7

According to the AAPCS, which of the following statements is TRUE with regard to preservation of register values by a function?

A.

A function must preserve R0-R3 and R12

B.

A function must preserve R4-R11 andR13

C.

No registers may be corrupted by any function

D.

All registers may be corrupted by any function

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Question # 8

Consider a sequence of five independent instructions running on a pipelined processor. There are no interlocks and no data dependencies between instructions, and each instruction takes one cycle to execute. The processor has three pipeline stages and is not superscalar.

How many cycles does it take to fetch, decode and execute all five instructions in sequence, assuming that there are no pipeline stalls?

A.

5 cycles

B.

7 cycles

C.

8 cycles

D.

15 cycles

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Question # 9

Which ARMv7 instructions are recommended to implement a semaphore?

A.

SWP, SWPB

B.

TEQ, TST

C.

STC, SBC

D.

LDREX, STREX

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Question # 10

A standard performance benchmark is being run on a single core ARM v7-A processor. The performance results reported are significantly lower than expected. Which of the following options is a possible explanation?

A.

L1 Caches and branch prediction are disabled

B.

The Embedded Trace Macrocell (ETM) is disabled

C.

The Memory Management Unit (MMU) is enabled

D.

The Snoop Control Unit (SCU) is disabled

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Question # 11

Which of the following memory attributes, specified in a translation table entry, could be used to protect a page containing a read-sensitive peripheral from speculative instruction fetches?

A.

S (Secure)

B.

nG (non-Global)

C.

xN (Execute Never)

D.

AP (Access Permission)

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Question # 12

In Architecture ARMv7-A which one of the following has a known physical address at power-on reset?

A.

The exception vector table

B.

The Memory Management Unit (MMU) translation table

C.

The Stack Pointer (SP)

D.

The System Control Register (SCTLR)

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Question # 13

When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?

A.

The linker

B.

The archiver

C.

The compiler

D.

The assembler

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Question # 14

Which of the following ARM processors has a superscalar micro architecture?

A.

ARM926EJ-S

B.

Cortex-M0

C.

Cortex-M3

D.

Cortex-A8

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Question # 15

Which one of the following debug methods is the least intrusive for analyzing a timing related bug?

A.

Place breakpoints on strategic locations to locate the problem area

B.

Instrument the code with print statements to locate the problem area

C.

Use debug hardware to place watchpoints on strategic data memory locations

D.

Use trace hardware to capture a trace log up to the point of the crash

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Question # 16

Within the ARMv7 architecture, which one of the following features is unique to the ARMv7-A profile?

A.

Cache support

B.

Privileged execution

C.

The ARM instruction set

D.

Virtual memory support

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Question # 17

Which of the following is a REQUIRED feature in the ARMv7 architecture?

A.

The Thumb-2 instruction set

B.

NEON

C.

Integer division instructions

D.

A memory management unit

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Question # 18

An advantage of removable flash memory over built-in flash memory is that:

A.

Storage can be easily replaced, for example to increase capacity.

B.

It is quicker to access, providing far greater bandwidth for read operations.

C.

It has a longer life, indicated by being rated for a higher number of write cycles.

D.

It takes up less physical space in a device, and does not require any space on the printed circuit board.

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Question # 19

According to the EABI. what would the C size of () operator return when given the following structure?

A.

19

B.

20

C.

24

D.

28

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Question # 20

In an ARMv7-A processor, with which level of the memory system is the Memory Management Unit (MMU) associated?

A.

Level 1

B.

Level 2

C.

Level 3

D.

Level 4

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Question # 21

What is the maximum value of the immediate field in an ARM SVC instruction?

A.

0x0

B.

0xF

C.

0xFF

D.

0xFFFFFF

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Question # 22

Which of the following is an accurate description of network storage as compared to on-chip RAM?

A.

It has lower capacity

B.

It is quicker to access

C.

It is always available

D.

It is easy to share with other devices

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Question # 23

In a single-processor system, which of these operations requires a barrier instruction to guarantee correct operation?

A.

Copying data from Flash to RAM

B.

Changing from one privileged mode to another

C.

Loading code into memory and then executing it

D.

Incrementing a RAM location that will be read by an interrupt handler

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Question # 24

Which of the following functions can be performed by a spinlock?

A.

Encrypting sensitive data on a network

B.

Preventing interrupts from being received by a CPU

C.

Preventing unauthorized access to an ARM powered device

D.

Protecting a critical section or data structure from concurrent access

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Question # 25

A message passing system between two CPUs is implemented using data stored in a shared area of memory. To pass a message, the first CPU executes the instructions:

The second CPU receives the message using the instructions:

On both CPUs, r1 = 0x5000 and r2 = 0x6000. At which of the points A, B, C and D must Data Memory Barrier (DMB) instructions be placed in order to ensure messages are passed reliably and efficiently?

A.

A only

B.

C only

C.

B and C

D.

A and D

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Question # 26

A Programmer's View CPU model usually provides:

A.

Cycle-accurate simulation of the CPU.

B.

Instruction-accurate simulation of the CPU.

C.

Simulation of user-defined memory-mapped peripherals.

D.

Cycle-accurate simulation of the cache and memory system.

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Question # 27

Under which of the following circumstances would a DSB instruction be used?

A.

In a multi-threaded system, when two threads need to be synchronized at a particular point

B.

When accessing a peripheral, it is necessary to halt until the memory access is complete

C.

When it is necessary to temporarily disable interrupts while carrying out a particular memory access

D.

In a multiprocessor system, when it is necessary to halt one of the cores while the other completes a critical task

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Question # 28

In an ARMv7-A system, the following C function calculates a simple checksum for an input data packet of variable length. The checksum is defined to be the sum of all of the 16-bit data items in the packet modulo 65536. The parameter data_items contains the number of 2-byte data items in the packet, and it cannot be zero by design.

When using an ARM compiler, which TWO of the following optimizations could improve the performance of this code? (Choose two)

A.

Use a do/while loop instead of a for loop

B.

Change the type of sum to be an unsigned short

C.

Change the type of i to be an unsigned int

D.

Use signed variables instead of unsigned variables

E.

Declare sum as a global variable

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Question # 29

Which of the following will cause the ARM Compiler to target the Thumb instruction set?

A.

Compiling exception handlers

B.

Specifying a Thumb-capable processor (e.g. -cpu=Cortex-A9)

C.

Enabling Thumb code generation on the command line (--thumb)

D.

Configuring the compiler for maximum code density (-Ospace)

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Question # 30

The Performance Monitoring Unit (PMU) of a Cortex-A9 processor permits direct measurement of which one of the following?

A.

Cache Size

B.

Clock Speed

C.

Program size

D.

Numbers of instructions executed

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Question # 31

When linking with the standard C library, which library functions MUST be redefined in order to port your code to a new piece of production hardware?

A.

Functions that are not compliant with the ISO C library standard

B.

Functions that are not compliant with the 1985 IEEE 754 standard for binary floating-point arithmetic

C.

Target-dependent functions which use semihosting

D.

Functions called implicitly by the compiler

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